diff options
| author | Daniel Baluta <daniel.baluta@nxp.com> | 2018-11-28 18:09:20 +0200 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:35:44 +0800 |
| commit | 3ea798c3f0a3ac1a6679d2174b2db23c6e981d9f (patch) | |
| tree | 74347d6ba5323cf6ac07be856a594f68d7da4cf3 /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
| parent | e649fb840d21872c6a3d47376924608eafcf37b6 (diff) | |
MLK-20095-2: arm64: dts: Enable IRQ steer domain
When DSP power domain is powered up we also need to power up IRQ steer
domain in order to receive interrupts from Audio peripherals.
Now the PD hierarchy looks like this:
* pd_dsp_irqsteer
* pd_dsp_mu_A
* pd_dsp_mu_B
* pd_dsp_ram
* pd_dsp
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 30 |
1 files changed, 19 insertions, 11 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 635b1d230036..1da5b9f30119 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -903,30 +903,38 @@ }; }; - pd_dsp_mu_A: PD_DSP_MU_A { - reg = <SC_R_MU_13A>; + pd_dsp_irqsteer: PD_DSP_MU_A { + reg = <SC_R_IRQSTR_DSP>; #power-domain-cells = <0>; power-domains =<&pd_audio>; #address-cells = <1>; #size-cells = <0>; - pd_dsp_mu_B: PD_DSP_MU_B { - reg = <SC_R_MU_13B>; + pd_dsp_mu_A: PD_DSP_MU_A { + reg = <SC_R_MU_13A>; #power-domain-cells = <0>; - power-domains =<&pd_dsp_mu_A>; + power-domains =<&pd_dsp_irqsteer>; #address-cells = <1>; #size-cells = <0>; - pd_dsp_ram: PD_AUD_OCRAM { - reg = <SC_R_DSP_RAM>; + pd_dsp_mu_B: PD_DSP_MU_B { + reg = <SC_R_MU_13B>; #power-domain-cells = <0>; - power-domains =<&pd_dsp_mu_B>; + power-domains =<&pd_dsp_mu_A>; #address-cells = <1>; #size-cells = <0>; - pd_dsp: PD_AUD_DSP { - reg = <SC_R_DSP>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = <SC_R_DSP_RAM>; #power-domain-cells = <0>; - power-domains =<&pd_dsp_ram>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = <SC_R_DSP>; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; }; }; }; |