diff options
| author | Huang Chaofan <chaofan.huang@nxp.com> | 2018-08-15 15:58:10 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:33:27 +0800 |
| commit | 648b068a9058eb19ae05fe6ec53f2b102bac2a74 (patch) | |
| tree | fbd8a9d8dc80abe72d06f5302b75dc0c0b66175d /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
| parent | 8dfd457aa8d7ca9973dde3e2942a5b827e0916a5 (diff) | |
MLK-19226 VPU: Add support for i.MX8QM B0 vpu decoder and encoder
Add support for i.MX8QM B0 vpu decoder and encoder and it is compatiable
with i.MX8QXP B0 VPU.
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit f2d7823da29c55644299eea84a2e866ea188c698)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index ea5a8a330af6..c1420dc1b661 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1163,32 +1163,43 @@ }; }; - pd_vpu: PD_VPU { + pd_vpu: vpu-power-domain { compatible = "nxp,imx8-pd"; reg = <SC_R_VPU>; #power-domain-cells = <0>; #address-cells = <1>; #size-cells = <0>; - pd_vpu_core: VPU_CORE { - reg = <SC_R_VPUCORE>; + pd_vpu_mu_enc: VPU_ENC_MU { + reg = <SC_R_VPU_MU_1>; #power-domain-cells = <0>; power-domains =<&pd_vpu>; - }; + #address-cells = <1>; + #size-cells = <0>; - pd_vpu_enc: VPU_ENC { - reg = <SC_R_VPU_ENC_0>; - #power-domain-cells = <0>; - power-domains =<&pd_vpu_core>; + pd_vpu_enc: VPU_ENC { + reg = <SC_R_VPU_ENC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_enc>; + }; }; - pd_vpu_dec: VPU_DEC { - reg = <SC_R_VPU_DEC_0>; + pd_vpu_mu_dec: VPU_DEC_MU { + reg = <SC_R_VPU_MU_0>; #power-domain-cells = <0>; - power-domains =<&pd_vpu_core>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_dec: VPU_DEC { + reg = <SC_R_VPU_DEC_0>; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_dec>; + }; }; }; + pd_isi_ch0: PD_IMAGING { compatible = "nxp,imx8-pd"; reg = <SC_R_ISI_CH0>; |