diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-06-01 16:10:48 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:32:00 +0800 |
| commit | 7f6550487adc8d9e0a180a34e6bef20d201cfc8d (patch) | |
| tree | 9fa1268069ccd07efd1e8f8a0d63523b2b8bf3ec /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
| parent | bf5db2a332b104cae740796f5d07ddb627015fec (diff) | |
MLK-18477-1 arm64: fsl-imx8qm.dtsi: Add bypass and disp_sel clks for dpu
This patch adds bypass clocks and disp_sel clocks in the dpu nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 44dfffafa581..9b56b5112185 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1669,9 +1669,13 @@ "irq_dpr1"; clocks = <&clk IMX8QM_DC0_PLL0_CLK>, <&clk IMX8QM_DC0_PLL1_CLK>, + <&clk IMX8QM_DC0_BYPASS_0_DIV>, + <&clk IMX8QM_DC0_DISP0_SEL>, + <&clk IMX8QM_DC0_DISP1_SEL>, <&clk IMX8QM_DC0_DISP0_CLK>, <&clk IMX8QM_DC0_DISP1_CLK>; - clock-names = "pll0", "pll1", "disp0", "disp1"; + clock-names = "pll0", "pll1", "bypass0", + "disp0_sel", "disp1_sel", "disp0", "disp1"; assigned-clocks = <&clk IMX8QM_DC0_DISP0_SEL>, <&clk IMX8QM_DC0_DISP1_SEL>; assigned-clock-parents = <&clk IMX8QM_DC0_PLL0_CLK>, @@ -2133,9 +2137,13 @@ "irq_dpr1"; clocks = <&clk IMX8QM_DC1_PLL0_CLK>, <&clk IMX8QM_DC1_PLL1_CLK>, + <&clk IMX8QM_DC1_BYPASS_0_DIV>, + <&clk IMX8QM_DC1_DISP0_SEL>, + <&clk IMX8QM_DC1_DISP1_SEL>, <&clk IMX8QM_DC1_DISP0_CLK>, <&clk IMX8QM_DC1_DISP1_CLK>; - clock-names = "pll0", "pll1", "disp0", "disp1"; + clock-names = "pll0", "pll1", "bypass0", + "disp0_sel", "disp1_sel", "disp0", "disp1"; assigned-clocks = <&clk IMX8QM_DC1_DISP0_SEL>, <&clk IMX8QM_DC1_DISP1_SEL>; assigned-clock-parents = <&clk IMX8QM_DC1_PLL0_CLK>, |