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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-03-09 13:43:18 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2020-03-09 13:43:18 +0100
commit9a14a1f6284c0a5d3bbbb4ccfea8b6959ca63d83 (patch)
tree5c8e9c1cc4365cee43e407eb72871d5ba4b08357 /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
parentdc6fa31dd7b294f586a07d5929ae3765ddbf86f3 (diff)
parentcd7c926fa65431a20a044f55dbd7609beaffbe46 (diff)
Merge remote-tracking branch 'fslc/4.14-2.3.x-imx' into toradex_4.14-2.3.x-imx
Conflicts: arch/arm64/boot/dts/freescale/Makefile arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index 5be519799eb5..c85fd8aed9ad 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -490,24 +490,24 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_pcie1: PD_HSIO_PCIE_B {
- reg = <SC_R_PCIE_B>;
+ pd_serdes1: PD_HSIO_SERDES_1 {
+ reg = <SC_R_SERDES_1>;
#power-domain-cells = <0>;
power-domains =<&pd_pcie0>;
#address-cells = <1>;
#size-cells = <0>;
- pd_serdes1: PD_HSIO_SERDES_1 {
- reg = <SC_R_SERDES_1>;
- #power-domain-cells = <0>;
- power-domains =<&pd_pcie1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_sata0: PD_HSIO_SATA_0 {
- reg = <SC_R_SATA_0>;
+ pd_pcie1: PD_HSIO_PCIE_B {
+ reg = <SC_R_PCIE_B>;
#power-domain-cells = <0>;
power-domains =<&pd_serdes1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_sata0: PD_HSIO_SATA_0 {
+ reg = <SC_R_SATA_0>;
+ #power-domain-cells = <0>;
+ power-domains =<&pd_pcie1>;
};
};
};
@@ -4168,7 +4168,7 @@
<0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pd_pcie1>;
+ power-domains = <&pd_pcie0>;
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX1PCIEBX1SATA>;
hsio = <&hsio>;