diff options
| author | Clark Wang <xiaoning.wang@nxp.com> | 2019-01-03 17:36:45 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:35:58 +0800 |
| commit | a1204e3b0e7ad1a28b4422b0df01be16ff3a0c4a (patch) | |
| tree | 25b93bcb3adfe226d8a750d9ee3e248dc5a9aa4a /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
| parent | 361f388d363e92375d04c297902b88fa06ef8c67 (diff) | |
MLK-20060-5 dts: lpspi: add dma mode support
Add dma configurations in dts files, for imx7ulp and imx8qm.
There is no "edma0" node in fsl-imx8qm-mek(or lpddr4-arm2)-domu.dts.
lpspi0 node has been deleted in these dts files, so delete lpspi3 node.
Add edma0a and edma0d for lpspi0 and lpspi3, and enable lpspi0/3 for xen.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Fugang Duan <Fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 62 |
1 files changed, 56 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 5325b715ac0e..38a8edec61b2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1117,6 +1117,24 @@ reg = <SC_R_SPI_0>; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_LPSPI0_RX { + reg = <SC_R_DMA_0_CH0>; + power-domains =<&pd_dma_lpspi0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_LPSPI0_TX { + reg = <SC_R_DMA_0_CH1>; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpspi1: PD_DMA_SPI_1 { reg = <SC_R_SPI_1>; @@ -1132,6 +1150,24 @@ reg = <SC_R_SPI_3>; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan6: PD_LPSPI3_RX { + reg = <SC_R_DMA_0_CH6>; + power-domains =<&pd_dma_lpspi3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_LPSPI3_TX { + reg = <SC_R_DMA_0_CH7>; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_emvsim0: PD_DMA_EMVSIM_0 { reg = <SC_R_EMVSIM_0>; @@ -2980,7 +3016,9 @@ clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QM_SPI0_CLK>; assigned-clock-rates = <20000000>; - power-domains = <&pd_dma_lpspi0>; + power-domains = <&pd_dma0_chan1>; + dma-names = "tx","rx"; + dmas = <&edma0 1 0 0>, <&edma0 0 0 1>; status = "disabled"; }; @@ -2994,7 +3032,9 @@ clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QM_SPI3_CLK>; assigned-clock-rates = <60000000>; - power-domains = <&pd_dma_lpspi3>; + power-domains = <&pd_dma0_chan7>; + dma-names = "tx","rx"; + dmas = <&edma0 7 0 0>, <&edma0 6 0 1>; status = "disabled"; }; @@ -3129,7 +3169,11 @@ edma0: dma-controller@5a1f0000 { compatible = "fsl,imx8qm-edma"; - reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ + <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */ + <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ + <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */ @@ -3140,8 +3184,12 @@ <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ #dma-cells = <3>; - dma-channels = <10>; - interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + dma-channels = <14>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, @@ -3151,7 +3199,9 @@ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", "edma0-chan16-rx", "edma0-chan17-tx", "edma0-chan18-rx", "edma0-chan19-tx", |