diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-12 10:52:11 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2020-02-12 11:05:58 +0100 |
| commit | b952231dd1321bf516466c89eac48f3a22e2b3c9 (patch) | |
| tree | 82a12171a696af3592cd855726faac86261af3e3 /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
| parent | 3994ed223ab67211651ab700f0f2a660531233c6 (diff) | |
arm64: dts: fsl: lpspi2: add dma mode support
Follow commit 'a1204e3b0e7a dts: lpspi: add dma mode support' for lpspi2.
This requires a follow up to dtbs which delete the edma0 node in favour
of their own implementation.
Related to: #51387
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit 1ff8709cc875557d3ba3c105af3be6bd6033c122)
Fixed power-domain stuff after imx_4.14.98_2.3.0 resp. 4.14-2.3.x-imx
merge.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 2d016eaa9584..f8f17c9ed99b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1046,6 +1046,16 @@ #power-domain-cells = <0>; power-domains = <&pd_dma>; }; + pd_dma0_chan4: PD_LPSPI2_RX { + reg = <SC_R_DMA_0_CH4>; + power-domains =<&pd_dma>; + #power-domain-cells = <0>; + }; + pd_dma0_chan5: PD_LPSPI2_TX { + reg = <SC_R_DMA_0_CH5>; + power-domains =<&pd_dma>; + #power-domain-cells = <0>; + }; pd_dma_lpspi3: PD_DMA_SPI_3 { reg = <SC_R_SPI_3>; #power-domain-cells = <0>; @@ -2926,6 +2936,8 @@ assigned-clocks = <&clk IMX8QM_SPI2_CLK>; assigned-clock-rates = <24000000>; power-domains = <&pd_dma_lpspi2>; + dma-names = "tx","rx"; + dmas = <&edma0 5 0 0>, <&edma0 4 0 1>; status = "disabled"; }; @@ -3078,6 +3090,8 @@ compatible = "fsl,imx8qm-edma"; reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */ + <0x0 0x5a240000 0x0 0x10000>, /* channel4 LPSPI2 rx */ + <0x0 0x5a250000 0x0 0x10000>, /* channel5 LPSPI2 tx */ <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */ <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ @@ -3091,9 +3105,11 @@ <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ #dma-cells = <3>; - dma-channels = <14>; + dma-channels = <16>; interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, @@ -3107,6 +3123,7 @@ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan4-rx", "edma0-chan5-tx", "edma0-chan6-rx", "edma0-chan7-tx", "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", @@ -3114,6 +3131,7 @@ "edma0-chan18-rx", "edma0-chan19-tx", "edma0-chan20-rx", "edma0-chan21-tx"; pdomains = <&pd_dma0_chan0>, <&pd_dma0_chan1>, /* lpspi0 */ + <&pd_dma0_chan4>, <&pd_dma0_chan5>, /* lpspi2 */ <&pd_dma0_chan6>, <&pd_dma0_chan7>, /* lpspi3 */ <&pd_dma0_chan12>, <&pd_dma0_chan13>, /* lpuart0 */ <&pd_dma0_chan14>, <&pd_dma0_chan15>, /* lpuart1 */ |