diff options
author | Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> | 2020-01-21 16:13:49 -0600 |
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committer | Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> | 2020-01-23 10:03:52 -0600 |
commit | c73e8ea3d88fa32fe259f44a7388435e7b866206 (patch) | |
tree | dd18ff6cd28f0a1daf96611b0f59b74a20258e33 /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
parent | 79e127531e863ae4b83dae6df205cf7e381d5cf1 (diff) |
MLK-23258-3 dts: Fix PCIE suspend/resume issue
Fix the parent-child power domain dependency to handle different
PCIE usecases.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index c123d3587276..7a9cb5744c09 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -490,25 +490,26 @@ #address-cells = <1>; #size-cells = <0>; - pd_pcie1: PD_HSIO_PCIE_B { - reg = <SC_R_PCIE_B>; - #power-domain-cells = <0>; - power-domains =<&pd_pcie0>; - #address-cells = <1>; - #size-cells = <0>; + }; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = <SC_R_SERDES_1>; + #power-domain-cells = <0>; + power-domains =<&pd_serdes0>; + #address-cells = <1>; + #size-cells = <0>; - pd_serdes1: PD_HSIO_SERDES_1 { - reg = <SC_R_SERDES_1>; + pd_pcie1: PD_HSIO_PCIE_B { + reg = <SC_R_PCIE_B>; #power-domain-cells = <0>; - power-domains =<&pd_pcie1>; + power-domains =<&pd_serdes1>; #address-cells = <1>; #size-cells = <0>; - pd_sata0: PD_HSIO_SATA_0 { + pd_sata0: PD_HSIO_SATA_0 { reg = <SC_R_SATA_0>; #power-domain-cells = <0>; - power-domains =<&pd_serdes1>; - }; + power-domains =<&pd_pcie1>; }; }; }; @@ -4118,7 +4119,7 @@ <0 0 0 2 &gic 0 74 4>, <0 0 0 3 &gic 0 75 4>, <0 0 0 4 &gic 0 76 4>; - power-domains = <&pd_pcie1>; + power-domains = <&pd_pcie0>; fsl,max-link-speed = <3>; hsio-cfg = <PCIEAX1PCIEBX1SATA>; hsio = <&hsio>; |