arm64: dts: fsl: apalis-imx8qm: add initial device tree

Copied from toradex_imx_4.14.78_1.0.0_ga-bring_up.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

1 files changed, 57 insertions, 25 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index 8febc6a6205e..2d016eaa9584 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -2585,6 +2585,7 @@
 
 	adc0: adc@5a880000 {
 		compatible = "fsl,imx8qxp-adc";
+		#io-channel-cells = <1>;
 		reg = <0x0 0x5a880000 0x0 0x10000>;
 		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
@@ -2599,6 +2600,7 @@
 
 	adc1: adc@5a890000 {
 		compatible = "fsl,imx8qxp-adc";
+		#io-channel-cells = <1>;
 		reg = <0x0 0x5a890000 0x0 0x10000>;
 		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
@@ -2906,13 +2908,27 @@
 			 <&clk IMX8QM_SPI0_IPG_CLK>;
 		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
-		assigned-clock-rates = <20000000>;
+		assigned-clock-rates = <24000000>;
 		power-domains = <&pd_dma_lpspi0>;
 		dma-names = "tx","rx";
 		dmas = <&edma0 1 0 0>, <&edma0 0 0 1>;
 		status = "disabled";
 	};
 
+	lpspi2: lpspi@5a020000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a020000 0x0 0x10000>;
+		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_SPI2_CLK>,
+			 <&clk IMX8QM_SPI2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_SPI2_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpspi2>;
+		status = "disabled";
+	};
+
 	lpspi3: lpspi@5a030000 {
 		compatible = "fsl,imx7ulp-spi";
 		reg = <0x0 0x5a030000 0x0 0x10000>;
@@ -3348,12 +3364,14 @@
 	pwm0: pwm@5d000000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d000000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM0_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM0_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM0_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>,
+				  <&clk IMX8QM_PWM0_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm0>;
 		status = "disabled";
 	};
 
@@ -3361,84 +3379,98 @@
 	pwm1: pwm@5d010000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d010000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM1_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM1_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM1_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>,
+				  <&clk IMX8QM_PWM1_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm1>;
 		status = "disabled";
 	};
 
 	pwm2: pwm@5d020000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d020000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM2_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM2_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM2_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>,
+				  <&clk IMX8QM_PWM2_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm2>;
 		status = "disabled";
 	};
 
 	pwm3: pwm@5d030000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d030000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM3_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM3_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM3_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>,
+				  <&clk IMX8QM_PWM3_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm3>;
 		status = "disabled";
 	};
 
 	pwm4: pwm@5d040000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d040000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM4_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM4_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM4_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>,
+				  <&clk IMX8QM_PWM4_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm4>;
 		status = "disabled";
 	};
 
 	pwm5: pwm@5d050000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d050000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM5_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM5_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM5_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>,
+				  <&clk IMX8QM_PWM5_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm5>;
 		status = "disabled";
 	};
 
 	pwm6: pwm@5d060000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d060000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM6_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM6_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM6_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>,
+				  <&clk IMX8QM_PWM6_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm6>;
 		status = "disabled";
 	};
 
 	pwm7: pwm@5d070000 {
 		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
 		reg = <0x0 0x5d070000 0  0x10000>;
-		clocks = <&clk IMX8QM_PWM7_HF_CLK>,
+		clocks = <&clk IMX8QM_PWM7_IPG_MSTR_CLK>,
 			 <&clk IMX8QM_PWM7_HF_CLK>;
 		clock-names = "ipg", "per";
-		assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>;
-		assigned-clock-rates = <24000000>;
+		assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>,
+				  <&clk IMX8QM_PWM7_CLK>;
+		assigned-clock-rates = <24000000>, <24000000>;
 		#pwm-cells = <2>;
+		power-domains = <&pd_lsio_pwm7>;
 		status = "disabled";
 	};