diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-01-15 15:13:15 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-02-25 15:50:35 +0800 |
| commit | e7e4a80d6b9a233ab79bc63c19f41267c3dcfe3c (patch) | |
| tree | c5d47e84da20bbfc749bd2ab001e062c6b19747a /arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | |
| parent | 22b12c5f04d4a5b2247239ccdcf4d9f1e99826c6 (diff) | |
MLK-23233-2 dts: arm64: sata: add the clks into sata nodes
To avoid potential dump when access the PHY and MISC CRR registers.
Add the CRRS clocks into SATA node.
The codes are merged back from 4.19 to 4.14 refer to MLK-21695.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 58ca9fcd3540..b7733b1c3e19 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -4180,10 +4180,18 @@ <&clk IMX8QM_HSIO_PHY_X1_PCLK>, <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_SATA_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "per_clk0", "per_clk1", "per_clk2", + "per_clk3", "per_clk4", "per_clk5", "phy_pclk0", "phy_pclk1", "phy_apbclk"; hsio = <&hsio>; power-domains = <&pd_sata0>; |