diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2017-07-03 13:02:57 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:27:34 +0800 |
| commit | 11f013b2145d28fbb11f16e81fe0e3ca9824ec05 (patch) | |
| tree | 947b8973c821656191b17f3477d160d4dfc64172 /arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | |
| parent | ae29ddaf69cf0959b0acfeab4fe56657140a9c50 (diff) | |
MLK-15343-1 ARM: imx: enable pcieb on imx8qm
Based on base board, enable pcieb lane1, enlarge
the CFG mapping space.
HSIO configuration is 1 lane PCIEA, 1 lane PCIEB and SATA.
PHY configurations:
PHY_X2_0 <------> PCIEA 1 lane
PHY_X2_1 <------> PCIEB 1 lane
PHY_X1 <------> SATA
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 7f75aab587cf..6ce6a33980de 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -382,6 +382,14 @@ SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021 >; }; + + pinctrl_pcieb: pciebgrp{ + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021 + >; + }; }; }; @@ -751,3 +759,11 @@ reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; |