diff options
| author | Peng Fan <peng.fan@nxp.com> | 2018-09-29 13:54:42 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:34:24 +0800 |
| commit | 17cb93269cf141445a4f0b387bda91f7a16de426 (patch) | |
| tree | 215327c442450b2bb1715c5e2c3401dfbeb24a89 /arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts | |
| parent | d67822371c404a45fbf06f8d458da5d4cbc063f5 (diff) | |
MLK-19773 ARM64: dts support camera in DomU
Use ISI0-3 in DomU, use ISI4-7 in Dom0.
BuildInfo:
- SCFW a958746e, SECO-FW 31fabbff, IMX-MKIMAGE f244aefa, ATF 1590be0
- U-Boot 2018.03-00707-g884cada50b
Use `mx8_v4l2_cap_drm.out -cam 0xf` to test camera in Dom0 and DomU
after `systemctl stop weston`.
One remaing issue is that ISI_CH0 is the parent power domain,
if dom0 runtime power down this domain, DomU will camera will
panic.
Since there is an i2c controller passthrough, the orignal backend
pvi2c adapter idx will be changed to 0, so reflect that change
in domu.dts.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts | 109 |
1 files changed, 106 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts index e7d88a3bd30e..acc421cd939f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts @@ -133,7 +133,19 @@ SC_R_CAAM_JR2_OUT SC_R_CAAM_JR3 SC_R_CAAM_JR3_OUT - >; + /* Camera */ + SC_R_ISI_CH0 + SC_R_ISI_CH1 + SC_R_ISI_CH2 + SC_R_ISI_CH3 + SC_R_MIPI_0 + SC_R_MIPI_0_PWM_0 + SC_R_MIPI_0_I2C_0 + SC_R_MIPI_0_I2C_1 + SC_R_CSI_0 + SC_R_CSI_0_PWM_0 + SC_R_CSI_0_I2C_0 + >; pads = < /* i2c1_lvds1 */ SC_P_LVDS1_I2C1_SCL @@ -166,7 +178,11 @@ SC_P_LVDS1_I2C0_SDA SC_P_USDHC2_RESET_B >; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>, <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 29 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>, + <&gpio1 27 GPIO_ACTIVE_LOW>, + <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio4 29 GPIO_ACTIVE_LOW>; }; }; @@ -323,7 +339,7 @@ mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>, <&usdhc1 0x12>, <&usbotg1 0x11>, <&edma01 0x10>, <&cm41 0x09>, <&pciea 0x08>, - <&vpu_decoder 0x7>, <&crypto 0x6>; + <&vpu_decoder 0x7>, <&crypto 0x6>, <&isi_0 0x5>; }; &lvds_region2 { @@ -583,3 +599,90 @@ xen,passthrough; }; }; + +/* Camera */ +&img_pdma_0_lpcg { + xen,passthrough; +}; + +&img_pdma_1_lpcg { + xen,passthrough; +}; + +&img_pdma_2_lpcg { + xen,passthrough; +}; + +&img_pdma_3_lpcg { + xen,passthrough; +}; + +&mipi_csi_0_lpcg { + xen,passthrough; +}; + +&img_pxl_link_csi0_lpcg { + xen,passthrough; +}; + +&gpio0_mipi_csi0 { + xen,passthrough; +}; + +&irqsteer_csi0 { + xen,passthrough; +}; + +&isi_0 { + xen,passthrough; + #stream-id-cells = <1>; + iommus = <&smmu>; + fsl,sc_rsrc_id = <SC_R_ISI_CH0>, + <SC_R_ISI_CH1>, + <SC_R_ISI_CH2>, + <SC_R_ISI_CH3>; +}; + +&isi_1 { + xen,passthrough; +}; + +&isi_2 { + xen,passthrough; +}; + +&isi_3 { + xen,passthrough; +}; + +&mipi_csi_0 { + xen,passthrough; +}; + +&i2c0_mipi_csi0 { + xen,passthrough; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +&i2c0_mipi_csi1 { + status = "okay"; +}; |