MLK-19450-2 ARM64: dts: 8qm: support cm41 rpmsg with DomU

1. Dom0 dts include fsl-imx8qm-mek.dtsi
2. Add /memreserve/ according to reserved-memory no-map node, then
   xen will not use these memory. The memory region are used by
   vpu/dsp/rpmsg, so xen should not touch them.
3. correct dom0 cma area, CM4 has limitation that the max access address
   is 0xE0000000, so the alloc-ranges should consider the limitation,
   otherwise rpmsg dma allocation will alloc memory higher than
   0xE0000000 and M4 will crash.
4. Hook CM41 with SMMU, added the addresses the CM41 will access, then
   after SMMU enabled, CM41 could access the address. To support
   Rear-View Camera, CM41 is kicked off by SCU at very early stage,
   DomU memory almost has no chance to have machine address 0x90000000
   included which is the vring desc buffer. So we have to enable SMMU
   to let CM41 access the memory.
5. Since DomU Guest RAM0 base is moved to 0x80000000, Let's change DomU
   ip address space to their machine address, since there is no conflict
   now.
6. Add reserved-memory in DomU dts, we enabled xen xl to copy that
   to DomU dtb.
7. Mark PCI/VPU as xen,passthrough, but not supported in DomU now.
8. Add Pixel_combiner2 passthrough to make dpu2 display work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>

1 files changed, 92 insertions, 3 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts
index d4ae5b31fe28..db9f3f97384c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dom0.dts
@@ -12,10 +12,21 @@
  * GNU General Public License for more details.
  */
 
-#include "fsl-imx8qm-mek.dts"
+/dts-v1/;
+
+/memreserve/ 0x84000000 0x4000000;
+/memreserve/ 0x90000000 0x400000;
+/memreserve/ 0x90400000 0x2000000;
+/memreserve/ 0x92400000 0x2000000;
+/memreserve/ 0x94400000 0x1800000;
+
+#include "fsl-imx8qm-mek.dtsi"
 #include "fsl-imx8qm-xen.dtsi"
 
 / {
+	model = "Freescale i.MX8QM MEK DOM0";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
 	chosen {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -57,6 +68,7 @@
 				SC_R_MU_2A
 			>;
 			rsrcs = <
+				SC_R_MU_6A
 				SC_R_GPU_1_PID0
 				SC_R_GPU_1_PID1
 				SC_R_GPU_1_PID2
@@ -129,7 +141,7 @@
 			compatible = "shared-dma-pool";
 			reusable;
 			size = <0 0x28000000>;
-			alloc-ranges = <0 0xd0000000 0 0x28000000>;
+			alloc-ranges = <0 0xa0000000 0 0x40000000>;
 			linux,cma-default;
 		};
 	};
@@ -149,6 +161,46 @@
 		status = "disabled";
 	};
 
+	cm41: cm41@1 {
+		fsl,sc_rsrc_id = <SC_R_M4_1_PID0>,
+				 <SC_R_M4_1_PID1>,
+				 <SC_R_M4_1_PID2>,
+				 <SC_R_M4_1_PID3>,
+				 <SC_R_M4_1_PID4>;
+		#stream-id-cells = <1>;
+		iommus = <&smmu>;
+		xen,passthrough;
+	};
+
+	irqsteer_cm41: irqsteer_cm41@0x51080000 {
+		reg = <0x0 0x51080000 0x0 0x10000>;
+		xen,passthrough;
+	};
+
+	mu_rpmsg1_b: mu_rpmsg1_b@0x5d2a0000 {
+		reg = <0x0 0x5d2a0000 0x0 0x10000>;
+		xen,passthrough;
+	};
+};
+
+&mu_rpmsg1 {
+	xen,passthrough;
+};
+
+&rpmsg1 {
+	status = "disabled";
+};
+
+&mu_6_lpcg {
+	xen,passthrough;
+};
+
+&mu_6_lpcg_b {
+	xen,passthrough;
+};
+
+&mu_7_lpcg_b {
+	xen,passthrough;
 };
 
 &usbotg1_lpcg {
@@ -167,6 +219,19 @@
 	xen,passthrough;
 };
 
+/*
+ * DomU CM41 use this, but DomU OS not need this,
+ * because smmu is enabled for CM41, so need to
+ *create the lpuart2 mapping in SMMU
+ */
+&lpuart2 {
+	xen,passthrough;
+};
+
+&lpuart2_lpcg {
+	xen,passthrough;
+};
+
 &di_lvds1_lpcg {
 	xen,passthrough;
 };
@@ -186,7 +251,7 @@
 &smmu {
 	mmu-masters = <&dpu2 0x13>, <&gpu_3d1 0x15>,
 		      <&usdhc1 0x12>, <&usbotg1 0x11>,
-		      <&edma01 0x10>;
+		      <&edma01 0x10>, <&cm41 0x09>;
 };
 
 &lvds_region2 {
@@ -224,6 +289,10 @@
 	iommus = <&smmu>;
 };
 
+&pixel_combiner2 {
+	xen,passthrough;
+};
+
 &prg10 {
 	xen,passthrough;
 };
@@ -329,3 +398,23 @@
 	reg = <0x0 0x5b100000 0x0 0x1000>;
 	xen,passthrough;
 };
+
+&pciea {
+       xen,passthrough;
+};
+
+&pcieb {
+       xen,passthrough;
+};
+
+&dsp {
+       xen,passthrough;
+};
+
+&vpu_decoder {
+       xen,passthrough;
+};
+
+&vpu_encoder {
+       xen,passthrough;
+};