MLK-20095-1: arm64: dts: Enable DSP sound card on QM MEK

Pretty similar with QXP but now DSP is inside VPU subsystem.

Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>

1 files changed, 132 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts
new file mode 100644
index 000000000000..70e4d7e1013d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-dsp.dts
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright NXP 2018
+
+#include "fsl-imx8qm-mek.dts"
+
+/ {
+	sound-cs42888 {
+		status = "disabled";
+	};
+
+	sound {
+		status = "disabled";
+	};
+
+	dspaudio: dspaudio {
+		compatible = "fsl,dsp-audio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_esai0>;
+		clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>,
+			<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>,
+			<&clk IMX8QM_AUD_ASRC_0_IPG>,
+			<&clk IMX8QM_AUD_ASRC_0_MEM>,
+			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
+			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
+			<&clk IMX8QM_ACM_AUD_CLK0_SEL>,
+			<&clk IMX8QM_ACM_AUD_CLK1_SEL>;
+
+		clock-names = "bus", "mclk", "ipg", "mem",
+				"asrck_0", "asrck_1", "asrck_2", "asrck_3";
+		assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>,
+			<&clk IMX8QM_AUD_PLL0_DIV>,
+			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
+			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
+			<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>;
+		assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
+		assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
+		power-domains = <&pd_esai0>;
+		status = "okay";
+	};
+
+	sound-dsp {
+		compatible = "fsl,imx-dsp-audio";
+		model = "dsp-audio";
+		cpu-dai = <&dspaudio>;
+		audio-codec = <&cs42888>;
+		audio-platform = <&dsp>;
+	};
+};
+
+&edma2 {
+	compatible = "fsl,imx8qm-edma";
+	reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
+		<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
+		<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
+		<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
+		<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
+		<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
+		<0x0 0x59320000 0x0 0x10000>, /* sai4 rx */
+		<0x0 0x59330000 0x0 0x10000>; /* sai5 tx */
+	#dma-cells = <3>;
+	shared-interrupt;
+	dma-channels = <8>;
+	interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+			<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,/* sai4 */
+			<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;/* sai5 */
+	interrupt-names = "edma2-chan8-rx", "edma0-chan9-tx", /* spdif0 */
+			"edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
+			"edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
+			"edma2-chan18-tx", "edma2-chan19-rx"; /* sai4, sai5 */
+	status = "okay";
+};
+
+/delete-node/ &pd_dma2_chan6;
+
+&pd_asrc0 {
+	reg = <SC_R_ASRC_0>;
+	power-domains =<&pd_dma2_chan5>;
+	#power-domain-cells = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	pd_dma2_chan6: PD_ESAI_0_RX {
+		reg = <SC_R_DMA_2_CH6>;
+		power-domains =<&pd_asrc0>;
+		#power-domain-cells = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pd_dma2_chan7: PD_ESAI_0_TX {
+			reg = <SC_R_DMA_2_CH7>;
+			power-domains =<&pd_dma2_chan6>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_esai0: PD_AUD_ESAI_0 {
+				reg = <SC_R_ESAI_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dma2_chan7>;
+			};
+		};
+	};
+};
+
+&esai0 {
+	status = "disabled";
+};
+
+&asrc0 {
+	status = "disabled";
+};
+
+&sai1 {
+	status = "disabled";
+};
+
+&wm8960 {
+	status = "disabled";
+};
+
+&cs42888 {
+	assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
+			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
+			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
+			<&clk IMX8QM_AUD_MCLKOUT0>;
+	assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>;
+};