diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-11-26 13:17:14 +0200 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:35:27 +0800 |
| commit | 6dff6410c47f3333b3db8ecaef5434cda00464f2 (patch) | |
| tree | 3bc24366f5b3a606d93881674b451e454f793e28 /arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | |
| parent | debe6b1155bda5fcf6b52667bc2368ec8204fa59 (diff) | |
MA-12957: arm64: dts: imx8qm/qxp mek: Correct interrupts for adv7535
This patch fixes the interrupts used by ADV7535. Initial patch
configured the GPIO0 IO00 as IO pin for the DSI_INT, used by ADV7535,
but the correct one is IO01, since IO00 is used by PWM.
Fixes: c2f1eceb5629 ("arm64: dts: imx8qm/qxp mek: Configure interrupts
for adv7535")
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index d5f1472f39fd..a28078336c56 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -591,7 +591,7 @@ fsl,pins = < SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c - SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 0x00000020 + SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 0x00000020 >; }; @@ -599,7 +599,7 @@ fsl,pins = < SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c - SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 0x00000020 + SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 0x00000020 >; }; |