diff options
| author | Peng Fan <peng.fan@nxp.com> | 2018-04-17 13:23:42 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:25 +0800 |
| commit | 85a137ab46a21efc2db999fc1028c5c0cfd0b738 (patch) | |
| tree | 6f463ce0873f3c8be2b65df2dbe42400d0d75126 /arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi | |
| parent | 0733ead1511b7e78ee8165907998d9263162e5c9 (diff) | |
MLK-18046 ARM64: dts: pass-through edma0 channel14/15 and lpuart1
Passthrough EDMA0 Channel 14/15 and lpuart1 to DomU.
Delete the original edma0 node and introduce the other 5 nodes
to which contains two channels each node.
Currently the nodes are included in fsl-imx8qm-xen.dtsi.
The modem-reset node to support bluetooth is not introduced in DomU
dts, because gpio support has not been done.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi index 939914916178..64ee1cd8fa7c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi @@ -20,6 +20,66 @@ /delete-node/ wu; + edma00: dma-controller0@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx"; + status = "okay"; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + + edma02: dma-controller2@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx"; + status = "okay"; + }; + + edma03: dma-controller3@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx"; + status = "okay"; + }; + + edma04: dma-controller4@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx"; + status = "okay"; + }; + usbotg1_lpcg: usbotg1_lpcg@5b270000 { compatible = "fsl,imx8qm-usbotg1-lpcg"; reg = <0x0 0x5b270000 0x0 0x10000>; @@ -56,6 +116,8 @@ }; }; +/delete-node/ &edma0; + &mu { interrupt-parent = <&gic>; }; @@ -66,18 +128,22 @@ &lpuart1 { interrupt-parent = <&gic>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; }; &lpuart2 { interrupt-parent = <&gic>; + dmas = <&edma02 17 0 0>, <&edma02 16 0 1>; }; &lpuart3 { interrupt-parent = <&gic>; + dmas = <&edma03 19 0 0>, <&edma03 18 0 1>; }; &lpuart4 { interrupt-parent = <&gic>; + dmas = <&edma04 21 0 0>, <&edma04 20 0 1>; }; &usdhc1 { |