MLK-19450-2 ARM64: dts: 8qm: support cm41 rpmsg with DomU

1. Dom0 dts include fsl-imx8qm-mek.dtsi
2. Add /memreserve/ according to reserved-memory no-map node, then
   xen will not use these memory. The memory region are used by
   vpu/dsp/rpmsg, so xen should not touch them.
3. correct dom0 cma area, CM4 has limitation that the max access address
   is 0xE0000000, so the alloc-ranges should consider the limitation,
   otherwise rpmsg dma allocation will alloc memory higher than
   0xE0000000 and M4 will crash.
4. Hook CM41 with SMMU, added the addresses the CM41 will access, then
   after SMMU enabled, CM41 could access the address. To support
   Rear-View Camera, CM41 is kicked off by SCU at very early stage,
   DomU memory almost has no chance to have machine address 0x90000000
   included which is the vring desc buffer. So we have to enable SMMU
   to let CM41 access the memory.
5. Since DomU Guest RAM0 base is moved to 0x80000000, Let's change DomU
   ip address space to their machine address, since there is no conflict
   now.
6. Add reserved-memory in DomU dts, we enabled xen xl to copy that
   to DomU dtb.
7. Mark PCI/VPU as xen,passthrough, but not supported in DomU now.
8. Add Pixel_combiner2 passthrough to make dpu2 display work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Anson Huang <Anson.Huang@nxp.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
index 984e40cd5ef3..bd7bd526e77d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi
@@ -95,6 +95,11 @@
 		reg = <0x0 0x5a470000 0x0 0x10000>;
 	};
 
+	lpuart2_lpcg: lpcg@5a480000 {
+		compatible = "fsl,imx8qm-lpuart-lpcg";
+		reg = <0x0 0x5a480000 0x0 0x10000>;
+	};
+
 	di_lvds0_lpcg: lpcg@56243000 {
 		compatible = "fsl,imx8qm-di-lvds0-lpcg";
 		reg = <0x0 0x56243000 0x0 0x1000>;
@@ -114,6 +119,31 @@
 		compatible = "fsl,imx8qm-dc1-lpcg";
 		reg = <0x0 0x57010000 0x0 0x10000>;
 	};
+
+	mu_5_lpcg: lpcg@5d600000 {
+		compatible = "fsl,imx8qm-mu-lpcg";
+		reg = <0x0 0x5d600000 0x0 0x10000>;
+	};
+
+	mu_6_lpcg: lpcg@5d610000 {
+		compatible = "fsl,imx8qm-mu-lpcg";
+		reg = <0x0 0x5d610000 0x0 0x10000>;
+	};
+
+	mu_5_lpcg_b: lpcg@5d690000 {
+		compatible = "fsl,imx8qm-mu-lpcg";
+		reg = <0x0 0x5d690000 0x0 0x10000>;
+	};
+
+	mu_6_lpcg_b: lpcg@5d6a0000 {
+		compatible = "fsl,imx8qm-mu-lpcg";
+		reg = <0x0 0x5d6a0000 0x0 0x10000>;
+	};
+
+	mu_7_lpcg_b: lpcg@5d6b0000 {
+		compatible = "fsl,imx8qm-mu-lpcg";
+		reg = <0x0 0x5d6b0000 0x0 0x10000>;
+	};
 };
 
 /delete-node/ &edma0;