MLK-16442-3: dts: imx8qm: Add clock parents for DC clocks.

Adds dt settings for the dpu driver to set the default clock
parents
- PLL1 (dc0_pll0_clk) for dispay0 and PLL2(dc0_pll1_clk) for display1.
Functionality is not changed from dpu driver perspective as the same
parents for the display clocks were used before.

The resulting clock topology for dc0_disp1 is:

dc0_pll1_div                1            1  1188000000 0 0
    dc0_pll1_clk            2            2  1188000000 0 0
       dc0_disp1_sel        1            1  1188000000 0 0
          dc0_disp1_div     1            1   148500000 0 0
             dc0_disp1_clk  1            1   148500000 0 0

(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)

Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 9bc6d3885cab..701ff27a8172 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -1118,6 +1118,10 @@
 			 <&clk IMX8QM_DC0_DISP0_CLK>,
 			 <&clk IMX8QM_DC0_DISP1_CLK>;
 		clock-names = "pll0", "pll1", "disp0", "disp1";
+		assigned-clocks = <&clk IMX8QM_DC0_DISP0_SEL>,
+				  <&clk IMX8QM_DC0_DISP1_SEL>;
+		assigned-clock-parents = <&clk IMX8QM_DC0_PLL0_CLK>,
+					 <&clk IMX8QM_DC0_PLL1_CLK>;
 		power-domains = <&pd_dc0>;
 		status = "disabled";
 
@@ -1245,6 +1249,10 @@
 			 <&clk IMX8QM_DC1_DISP0_CLK>,
 			 <&clk IMX8QM_DC1_DISP1_CLK>;
 		clock-names = "pll0", "pll1", "disp0", "disp1";
+		assigned-clocks = <&clk IMX8QM_DC1_DISP0_SEL>,
+				  <&clk IMX8QM_DC1_DISP1_SEL>;
+		assigned-clock-parents = <&clk IMX8QM_DC1_PLL0_CLK>,
+					 <&clk IMX8QM_DC1_PLL1_CLK>;
 		power-domains = <&pd_dc1>;
 		status = "disabled";