diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-03-13 17:11:57 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:30:59 +0800 |
| commit | bb958654e36f0206c2bc2c496b4c5b6e76fa03e4 (patch) | |
| tree | eafa5ef7ffc86c83bbe3f5dece6edd0e908418b1 /arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | |
| parent | 780d853b0ca12bbf72b1b8903f831ffbb1fbff7b (diff) | |
MLK-17815-1 dts: arm64: imx8qm: add sata phy region
Add the extra imx8qm sata phy register region,
and the clock phy_apbclk, mandatory required to
access phy registers.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 1403df3cf042..585eb52f2919 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -3637,16 +3637,19 @@ sata: sata@5f020000 { compatible = "fsl,imx8qm-ahci"; - reg = <0x0 0x5f020000 0x0 0x10000>; /* Controller reg */ + reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */ + <0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */ + reg-names = "ctl", "phy"; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8QM_HSIO_SATA_CLK>, <&clk IMX8QM_HSIO_PHY_X1_PCLK>, <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, - <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>; + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", - "phy_pclk0", "phy_pclk1"; + "phy_pclk0", "phy_pclk1", "phy_apbclk"; hsio = <&hsio>; power-domains = <&pd_sata0>; iommus = <&smmu 0x13 0x7f80>; |