MLK-15284-1: arm64: dts: enable the GPMI NAND module in device tree

enable the GPMI NAND module in device tree for i.MX8QXP

Signed-off-by: Han Xu <han.xu@nxp.com>

1 files changed, 62 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts
new file mode 100644
index 000000000000..774a1dab6b24
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-gpmi-nand.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2017 NXP
+ *
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qxp-lpddr4-arm2.dts"
+
+&iomuxc {
+	imx8qxp-zebu {
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_NAND_READY_B	0x0e00004c
+				SC_P_EMMC0_DATA0_CONN_NAND_DATA00	0x0e00004c
+				SC_P_EMMC0_DATA1_CONN_NAND_DATA01	0x0e00004c
+				SC_P_EMMC0_DATA2_CONN_NAND_DATA02	0x0e00004c
+				SC_P_EMMC0_DATA3_CONN_NAND_DATA03	0x0e00004c
+				SC_P_EMMC0_DATA4_CONN_NAND_DATA04	0x0e00004c
+				SC_P_EMMC0_DATA5_CONN_NAND_DATA05	0x0e00004c
+				SC_P_EMMC0_DATA6_CONN_NAND_DATA06	0x0e00004c
+				SC_P_EMMC0_DATA7_CONN_NAND_DATA07	0x0e00004c
+				SC_P_EMMC0_STROBE_CONN_NAND_CLE		0x0e00004c
+				SC_P_EMMC0_RESET_B_CONN_NAND_WP_B	0x0e00004c
+
+				SC_P_USDHC1_DATA0_CONN_NAND_CE1_B	0x0e00004c
+				SC_P_USDHC1_DATA2_CONN_NAND_WE_B	0x0e00004c
+				SC_P_USDHC1_DATA3_CONN_NAND_ALE		0x0e00004c
+				SC_P_USDHC1_CMD_CONN_NAND_CE0_B		0x0e00004c
+				SC_P_USDHC1_VSELECT_CONN_NAND_RE_P	0x0e00004c
+				SC_P_USDHC1_WP_CONN_NAND_DQS_N		0x0e00004c
+				SC_P_USDHC1_CD_B_CONN_NAND_DQS_P	0x0e00004c
+				SC_P_USDHC1_RESET_B_CONN_NAND_RE_N	0x0e00004c
+			>;
+		};
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+};
+
+/* Disabled the usdhc2 since pin conflict */
+&usdhc2 {
+	status = "disabled";
+};