diff options
| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> | 2018-05-08 18:25:11 -0500 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:39 +0800 |
| commit | 0fff91b01376dfc3abb680428c4a5bc8259ab2c8 (patch) | |
| tree | 16765f77b9e537b4efb562ccc81f66cdf04e178e /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | |
| parent | e1314b06c40f30feabcded650ee27b653ee3099f (diff) | |
MLK-18220-5 dts:imx8qxp Remove all clock references from GPIO device entries.
Controlling GPIO clocks in iMX8 is dependent on power domain,
and an unused GPIO's power domain is disabled during startup.
This makes it difficult for the GPIO driver to manage clocks for such
GPIOs. This causes failures during system suspend/resume when
GPIO registers are saved/restored.
These LPCG clocks will be always be in an enabled state, similar
to earlier iMX processors.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index 8303704ba1f4..520879f1c6ea 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -1364,7 +1364,7 @@ interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_CSI0_IPG_CLK>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; clock-names = "ipg"; power-domains = <&pd_mipi_csi>; }; @@ -2093,7 +2093,7 @@ <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&irqsteer_csi>; - clocks = <&clk IMX8QXP_CSI0_APB_CLK>, + clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_CSI0_CORE_CLK>, <&clk IMX8QXP_CSI0_ESC_CLK>, <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; @@ -2327,8 +2327,6 @@ power-domains = <&pd_lsio_gpio0>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO0_IPG_S_CLK>; - clock-names = "ipg"; }; gpio1: gpio@5d090000 { @@ -2340,8 +2338,6 @@ power-domains = <&pd_lsio_gpio1>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO1_IPG_S_CLK>; - clock-names = "ipg"; }; gpio2: gpio@5d0a0000 { @@ -2353,8 +2349,6 @@ power-domains = <&pd_lsio_gpio2>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO2_IPG_S_CLK>; - clock-names = "ipg"; }; gpio3: gpio@5d0b0000 { @@ -2366,8 +2360,6 @@ power-domains = <&pd_lsio_gpio3>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO3_IPG_S_CLK>; - clock-names = "ipg"; }; gpio4: gpio@5d0c0000 { @@ -2379,8 +2371,6 @@ power-domains = <&pd_lsio_gpio4>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO4_IPG_S_CLK>; - clock-names = "ipg"; }; gpio5: gpio@5d0d0000 { @@ -2392,8 +2382,6 @@ power-domains = <&pd_lsio_gpio5>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO5_IPG_S_CLK>; - clock-names = "ipg"; }; gpio6: gpio@5d0e0000 { @@ -2405,8 +2393,6 @@ power-domains = <&pd_lsio_gpio6>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO6_IPG_S_CLK>; - clock-names = "ipg"; }; gpio7: gpio@5d0f0000 { @@ -2418,8 +2404,6 @@ power-domains = <&pd_lsio_gpio7>; interrupt-controller; #interrupt-cells = <2>; - clocks = <&clk IMX8QXP_LSIO_GPIO7_IPG_S_CLK>; - clock-names = "ipg"; }; gpio0_mipi_csi0: gpio@58222000 { @@ -2432,8 +2416,6 @@ interrupt-controller; #interrupt-cells = <2>; power-domains = <&pd_mipi_csi>; - clocks = <&clk IMX8QXP_CSI0_IPG_CLK_S>; - clock-names = "ipg"; }; gpu_3d0: gpu@53100000 { |