diff options
| author | Yuchou Gan <yuchou.gan@nxp.com> | 2018-04-20 23:15:50 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:26 +0800 |
| commit | 152978fb16d342593edfdee5d9206ea094f3b033 (patch) | |
| tree | f6f269df610a5c74fb5176b389b61a7a72a5a6b6 /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | |
| parent | c3d83d78eacc3c7212398b75ee978734b4630e11 (diff) | |
MLK-18101-2 arm64: dtsi: fsl-imx8qxp: Add prg1 for dpr1_channel2
On QXP B0 board, prg1 can alternative connect to
dpr_channel1 and channel2. And if enable PRG0_SEL:BLIT0,
prg1 will connect to channel2, so it could
support 2-plane format tile to linear convert.
Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index da9b90ba828b..ff349f7e49ed 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -1183,7 +1183,7 @@ "fsl,imx8qm-dpr-channel"; reg = <0x0 0x560e0000 0x0 0x10000>; fsl,sc-resource = <SC_R_DC_0_BLIT1>; - fsl,prgs = <&prg2>; + fsl,prgs = <&prg2>, <&prg1>; clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, <&clk IMX8QXP_DC0_DPR0_B_CLK>, <&clk IMX8QXP_DC0_RTRAM0_CLK>; |