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authorFugang Duan <fugang.duan@nxp.com>2017-12-20 17:54:33 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:30:02 +0800
commit2f7fc0a65902caa3b09110b5907f3bd819ac12f8 (patch)
treed6efedeb1df7ac00a61ab963a68872fe152d6aa9 /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
parentcb1a9503aa1bcc475add3be37d9e2d2f04db1854 (diff)
MLK-17290-06 arm64: dts: gpio: add mipi csi SS gpio clock and power domain
GPIO in MIPI CSI SS also has its related ipg clock and power domain, add them. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Tested-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index f00d9e06ff9e..7841904f660f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -1918,6 +1918,11 @@
interrupt-parent = <&irqsteer_csi>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ power-domains = <&pd_mipi_csi>;
+ clocks = <&clk IMX8QXP_CSI0_IPG_CLK_S>;
+ clock-names = "ipg";
};
gpu_3d0: gpu@53100000 {