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authorAnson Huang <Anson.Huang@nxp.com>2018-05-08 10:25:49 +0800
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:31:36 +0800
commit382096517222f418729288b99e107c6e1b4e2aee (patch)
tree70ff243d368282efff54c8626f0b678a0de7daa1 /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
parentaff7773a32d3a469f83928cb6c44604da98f0493 (diff)
MLK-18224-2 ARM64: dts: freescale: imx8qxp: update MU IRQ number
MU IRQ number is incorrect, update it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
index 28f6e17ee192..0bbd3fc8ca04 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
@@ -117,7 +117,7 @@
mu: mu@5d1c0000 {
compatible = "fsl,imx8-mu";
reg = <0x0 0x5d1c0000 0x0 0x10000>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&wu>;
fsl,scu_ap_mu_id = <0>;
status = "okay";