diff options
| author | Robin Gong <yibin.gong@nxp.com> | 2018-05-09 00:45:03 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:38 +0800 |
| commit | b6f4e17b6f91ffd757546a0ceb616dac24c55ad4 (patch) | |
| tree | ceec3e45cb2f81ff93d7aaf996eacb6187a4391d /arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | |
| parent | 7b11f89073fe56f463bb0bbd8c63b04411aeca1e (diff) | |
MLK-18241-2: ARM64: dts: freescale: imx8qxp: add edma channel power domain for LPUART
Add edma channel power domain for LPUART to make sure the specific
edma channel power up in dma mode.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 60 |
1 files changed, 57 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index a49aaed871f5..d40de913fb1c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -647,19 +647,73 @@ reg = <SC_R_UART_1>; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; wakeup-irq = <226>; + + pd_dma2_chan10: PD_UART1_RX { + reg = <SC_R_DMA_2_CH10>; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan11: PD_UART1_TX { + reg = <SC_R_DMA_2_CH11>; + power-domains =<&pd_dma2_chan10>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpuart2: PD_DMA_UART2 { reg = <SC_R_UART_2>; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; wakeup-irq = <227>; + + pd_dma2_chan12: PD_UART2_RX { + reg = <SC_R_DMA_2_CH12>; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = <SC_R_DMA_2_CH13>; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpuart3: PD_DMA_UART3 { reg = <SC_R_UART_3>; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; wakeup-irq = <228>; + + pd_dma3_chan14: PD_UART3_RX { + reg = <SC_R_DMA_2_CH14>; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan15: PD_UART3_TX { + reg = <SC_R_DMA_2_CH15>; + power-domains =<&pd_dma3_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpspi0: PD_DMA_SPI_0 { reg = <SC_R_SPI_0>; @@ -2218,7 +2272,7 @@ clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_UART1_CLK>; assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart1>; + power-domains = <&pd_dma2_chan11>; dma-names = "tx","rx"; dmas = <&edma2 11 0 0>, <&edma2 10 0 1>; @@ -2235,7 +2289,7 @@ clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_UART2_CLK>; assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart2>; + power-domains = <&pd_dma2_chan13>; dma-names = "tx","rx"; dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; @@ -2252,7 +2306,7 @@ clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_UART3_CLK>; assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart3>; + power-domains = <&pd_dma3_chan15>; dma-names = "tx","rx"; dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; |