LF-387-4 usb: dwc3: Add cache type configuration support

This feature is telling how to configure cache type on 4 different
transfer types: Data Read, Desc Read, Data Write and Desc write. For each
treasfer type, controller has a 4-bit register field to enable different
cache type. Quoted from DWC3 data book Table 6-5 Cache Type Bit Assignments:
----------------------------------------------------------------
MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
----------------------------------------------------------------
AHB      |Cacheable     |Bufferable   |Privilegge |Data
AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
----------------------------------------------------------------
Note: The AHB, AXI3, AXI4, and PCIe busses use different names for certain
signals, which have the same meaning:
  Bufferable = Posted
  Cacheable = Modifiable = Snoop (negation of No Snoop)

In most cases, driver support is not required unless the default values of
registers are not correct *and* DWC3 node has enabled dma-coherent. So far we
have observed USB device detect failure on some Layerscape platforms if this
programming was not applied.

Related struct:
struct dwc3_cache_type {
	u8 transfer_type_datard;
	u8 transfer_type_descrd;
	u8 transfer_type_datawr;
	u8 transfer_type_descwr;
};

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>

0 files changed, 0 insertions, 0 deletions