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authorAndre Przywara <andre.przywara@arm.com>2020-08-28 14:05:56 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-10-13 10:08:19 +0200
commit1b9f0d242ab6d4a9c30a6d6808718ebb9f79e453 (patch)
tree21eb77b68528a227643fcba1e8529d2e0487c3be /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
parent27e53e23a3cef73a6aac9a776685af1bebca0565 (diff)
arm64: dts: freescale: Fix SP805 clock-names
[ Upstream commit f2dc2359b75e1fd345fd710862f73db20dc55864 ] The SP805 binding sets the order of the clock-names to be: "wdog_clk", "apb_pclk" (in exactly that order). Change the order in the DTs for Freescale platforms to match that. The two clocks given in all nodes are actually the same, so that does not change any behaviour. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 5716ac20bddd..963091069ab3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -496,14 +496,14 @@
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
- clock-names = "apb_pclk", "wdog_clk";
+ clock-names = "wdog_clk", "apb_pclk";
};
cluster1_core1_watchdog: watchdog@c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen 4 15>, <&clockgen 4 15>;
- clock-names = "apb_pclk", "wdog_clk";
+ clock-names = "wdog_clk", "apb_pclk";
};
sai1: audio-controller@f100000 {