diff options
| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2019-11-29 03:07:14 +0200 |
|---|---|---|
| committer | Claudiu Manoil <claudiu.manoil@nxp.com> | 2019-11-29 13:53:46 +0200 |
| commit | 51eb297b8e61b30cab85a4f6299f2390f9d3151a (patch) | |
| tree | eb4e95177879d880da9bce9ac78fdb5120a92a64 /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | |
| parent | a3f97ef8b285ab3e824525a25d45df7900b6bb43 (diff) | |
arm64: dts: fsl: Specify phy-mode for CPU ports
PHYLINK requires that device tree nodes have a phy-mode or
phy-connection-type property. The internal Felix ports really are
connected to the ENETC via 2 back-to-back MACs, so the correct MII type
is GMII (one of which is overclocked at 2.5Gbaud, but still GMII).
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 27fd283f48ff..9044f05dc4de 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -789,6 +789,8 @@ /* internal to-cpu ports */ port@4 { reg = <4>; + phy-mode = "gmii"; + fixed-link { speed = <1000>; full-duplex; @@ -797,6 +799,8 @@ port@5 { reg = <5>; ethernet = <&enetc_port3>; + phy-mode = "gmii"; + fixed-link { speed = <1000>; full-duplex; |