diff options
| author | Alison Wang <alison.wang@nxp.com> | 2019-12-12 15:35:32 +0800 |
|---|---|---|
| committer | Alison Wang <alison.wang@nxp.com> | 2019-12-23 15:46:15 +0800 |
| commit | a03628f1a668d013bdcc2cc3949e74c143ecd2e1 (patch) | |
| tree | f8bbb1201ab03a702da8bc1f0387d34a04a93618 /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | |
| parent | de1a87b02a2d9d132bea4fbe566e456393d843c5 (diff) | |
LF-403 ARM64: dts: fsl: Add clock-names mclk0 for SAI nodes
This patch adds clock-names "mclk0" to match with the current SAI
driver.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 7de30603b708..19afdd098167 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -538,8 +538,9 @@ reg = <0x0 0xf100000 0x0 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 4>, <&edma0 1 3>; @@ -552,8 +553,9 @@ reg = <0x0 0xf110000 0x0 0x10000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 6>, <&edma0 1 5>; @@ -566,8 +568,9 @@ reg = <0x0 0xf130000 0x0 0x10000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clockgen 4 1>, <&clockgen 4 1>, - <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 10>, <&edma0 1 9>; |