diff options
author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-04 16:13:48 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:50 +0800 |
commit | 5b6c64df1e7f90a17ad6785c4c43b2bd258ffa46 (patch) | |
tree | cd1bb91329586fc45268f7cdea49e5dffcb7106f /arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | |
parent | 864cef80b1bb501f87d11feb110498542bd4666e (diff) |
arm64: dts: imx8: add adma lpcg clocks
Add adma lpcg clocks
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 63590b6ffaf7..690dc02c20c7 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -4,12 +4,22 @@ * Dong Aisheng <aisheng.dong@nxp.com> */ +#include <dt-bindings/firmware/imx/rsrc.h> + adma_subsys: bus@59000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x2000000>; + dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; + }; + + /* LPCG clocks */ adma_lpcg: clock-controller@59000000 { compatible = "fsl,imx8qxp-lpcg-adma"; reg = <0x59000000 0x2000000>; @@ -221,6 +231,50 @@ adma_subsys: bus@59000000 { status = "disabled"; }; + uart0_lpcg: clock-controller@5a460000 { + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART0_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_0>; + }; + + uart1_lpcg: clock-controller@5a470000 { + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART1_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_1>; + }; + + uart2_lpcg: clock-controller@5a480000 { + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART2_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_2>; + }; + + uart3_lpcg: clock-controller@5a490000 { + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_UART3_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_UART_3>; + }; + adma_i2c0: i2c@5a800000 { reg = <0x5a800000 0x4000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; @@ -664,4 +718,48 @@ adma_subsys: bus@59000000 { power-domains = <&pd IMX_SC_R_MQS_0>; status = "disabled"; }; + + i2c0_lpcg: clock-controller@5ac00000 { + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C0_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_0>; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C1_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_1>; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C2_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_2>; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_ADMA_I2C3_CLK>, + <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_I2C_3>; + }; }; |