diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-08-20 17:40:36 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:24 +0800 |
| commit | 22fcb18ab6f3675006d7a1c49d9f7be45f56eca0 (patch) | |
| tree | 9fb88d6d283905b0bca5418ee711ed6170c92a81 /arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | |
| parent | b145d49e14398bd1b22a2cd7ee1c119ee612718a (diff) | |
arm64: imx8-ss-dc0/1.dtsi: Use dc0/1_disp_lpcg clocks as disp0/1 clocks of dpu0/1
This patch uses dc0/1_disp_lpcg clocks as disp0/1 clocks of dpu0/1.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi index 85df8651906c..5ccac755176c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -283,8 +283,7 @@ dc0_subsys: bus@56000000 { clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, - <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, - <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + <&dc0_disp_lpcg 0>, <&dc0_disp_lpcg 1>; clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1"; power-domains = <&pd IMX_SC_R_DC_0>, <&pd IMX_SC_R_DC_0_PLL_0>, |