diff options
| author | Xianzhong <xianzhong.li@nxp.com> | 2019-09-06 06:25:35 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2021-11-02 16:52:26 +0800 |
| commit | 78959f0a94a94d375adf45bf81919a6459efc14e (patch) | |
| tree | b4466cbb43e9129c7e89ea4804fc3905d7e4c488 /arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | |
| parent | 9ea1f5ffd50d4c97690cd1bd3e9cc478dd22a8e6 (diff) | |
arm64: dts: imx8qm/qxp: add dpr support for bliteng
add dpr channel 1 and 2 to support DPU blit engine
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi index 8e5c914c776a..1558cacb4508 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -339,6 +339,8 @@ dc0_subsys: bus@56000000 { <&pd IMX_SC_R_DC_0_PLL_0>, <&pd IMX_SC_R_DC_0_PLL_1>; power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, + <&dc0_dpr1_channel2>; status = "disabled"; }; }; |