diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-08-08 13:06:11 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:45 +0800 |
| commit | ed49c29a999e381ccb30d94cdc144130bc50fe5b (patch) | |
| tree | 008daad328fbcf48351179568d0d9bc0d39d8929 /arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | |
| parent | ef80f59c77d4776b7309bf111cb50ab6aedb4933 (diff) | |
arm64: imx8-ss-dc0/1.dtsi: Add common dpu clocks
Currently, all DPUs in i.MX8qm/qxp have the same clocks - pll0/1,
bypass0 and disp0/1. So add the common clocks in imx8-ss-dc0/1.dtsi.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi index 6de96872c151..d18956d5c284 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc0.dtsi @@ -269,6 +269,12 @@ dc0_subsys: bus@56000000 { "framegen1_primsync_off", "framegen1_secsync_on", "framegen1_secsync_off"; + clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_DC_0_VIDEO0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>; + clock-names = "pll0", "pll1", "bypass0", "disp0", "disp1"; power-domains = <&pd IMX_SC_R_DC_0>, <&pd IMX_SC_R_DC_0_PLL_0>, <&pd IMX_SC_R_DC_0_PLL_1>; |