diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-11-11 10:15:02 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:35 +0800 |
| commit | 672cfd49a3460d0464991cef4e5ee5337ee55a51 (patch) | |
| tree | af88bd523a1efa88860cf18cd43d67957905c032 /arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | |
| parent | 0ba94b8535870ddf4444b69af06bf06f73deb881 (diff) | |
arm64: imx8-ss-dc1.dtsi: Add dc1_dpr1_channel3 and dc1_dpr2_channel1-3 support
This patch adds dc1_dpr1_channel3 and dc1_dpr2_channel1-3 device tree
nodes support for i.MX8 DC1 subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index d895656801d5..42b91604fd81 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -334,6 +334,62 @@ dc1_subsys: bus@57000000 { status = "disabled"; }; + dc1_dpr1_channel3: dpr-channel@570f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x570f0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_FRAC0>; + fsl,prgs = <&dc1_prg3>; + clocks = <&dc1_dpr0_lpcg 0>, + <&dc1_dpr0_lpcg 1>, + <&dc1_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel1: dpr-channel@57100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57100000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_VIDEO0>; + fsl,prgs = <&dc1_prg4>, <&dc1_prg5>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel2: dpr-channel@57110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57110000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_VIDEO1>; + fsl,prgs = <&dc1_prg6>, <&dc1_prg7>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + + dc1_dpr2_channel3: dpr-channel@57120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x57120000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_1_WARP>; + fsl,prgs = <&dc1_prg8>, <&dc1_prg9>; + clocks = <&dc1_dpr1_lpcg 0>, + <&dc1_dpr1_lpcg 1>, + <&dc1_rtram1_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_1>; + status = "disabled"; + }; + dpu2: dpu@57180000 { #address-cells = <1>; #size-cells = <0>; |