diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-08-20 17:33:04 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:35 +0800 |
| commit | 6cc83bcf29b4ac89780ec5aede662c4613fdf132 (patch) | |
| tree | cbd62ee236e9ca51d1f998a70f95088b82bf3c9d /arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | |
| parent | ea334b7f6404bbe239a84cebd6e2399939e31f66 (diff) | |
arm64: imx8-ss-dc0/1.dtsi: Add dc0/1_displ_lpcg clocks
This patch adds dc0/1_displ_lpcg clocks to DC0/1 subsystem device trees.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index 2716ca4a7c08..d2803725f7f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -31,6 +31,17 @@ dc1_subsys: bus@57000000 { clock-output-names = "dc1_axi_ext_clk"; }; + dc1_disp_lpcg: clock-controller@57010000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x57010000 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>, + <&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>; + bit-offset = <0 4>; + clock-output-names = "dc1_disp0_lpcg_clk", "dc1_disp1_lpcg_clk"; + power-domains = <&pd IMX_SC_R_DC_1>; + }; + dc1_dpr0_lpcg: clock-controller@57010018 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x57010018 0x4>; |