diff options
| author | Xianzhong <xianzhong.li@nxp.com> | 2019-09-06 06:25:35 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:27 +0800 |
| commit | 856d77391685d345821d9625e6660e5b45052255 (patch) | |
| tree | 878f9aaf95c6264f3cc56a52ca8ec9881f206fd0 /arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | |
| parent | 947f519f08b0f3c95fb99b7db4bdd79b2c494bc4 (diff) | |
arm64: dts: imx8qm/qxp: add dpr support for bliteng
add dpr channel 1 and 2 to support DPU blit engine
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi index 135c0078030b..58253823005a 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dc1.dtsi @@ -340,6 +340,8 @@ dc1_subsys: bus@57000000 { <&pd IMX_SC_R_DC_1_PLL_0>, <&pd IMX_SC_R_DC_1_PLL_1>; power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc1_dpr1_channel1>, + <&dc1_dpr1_channel2>; status = "disabled"; }; }; |