diff options
author | Clark Wang <xiaoning.wang@nxp.com> | 2020-04-20 14:08:00 +0800 |
---|---|---|
committer | Clark Wang <xiaoning.wang@nxp.com> | 2020-04-28 16:07:44 +0800 |
commit | 6f2f0eaaa6de1dcf7d80553116fc8367404dd308 (patch) | |
tree | a6fb8ec8454ffc3334fb331ebce6eaffe17d1a87 /arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | |
parent | a8c6bccf7d0cf4834a55221510a0f0dbddd5aaf5 (diff) |
MLK-23865 ARM64: dts: enable dma support for lpspi
Add DMA configurations for LPSPI nodes on i.MX8QX/QM/DXL.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 50 |
1 files changed, 44 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index dab01d97a3ef..5e2cc2787716 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -32,6 +32,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <20000000>; power-domains = <&pd IMX_SC_R_SPI_0>; + dma-names = "tx","rx"; + dmas = <&edma2 1 0 0>, <&edma2 0 0 1>; status = "disabled"; }; @@ -48,6 +50,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; power-domains = <&pd IMX_SC_R_SPI_2>; + dma-names = "tx","rx"; + dmas = <&edma2 5 0 0>, <&edma2 4 0 1>; status = "disabled"; }; @@ -64,6 +68,8 @@ dma_subsys: bus@5a000000 { assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <60000000>; power-domains = <&pd IMX_SC_R_SPI_3>; + dma-names = "tx","rx"; + dmas = <&edma2 7 0 0>, <&edma2 6 0 1>; status = "disabled"; }; @@ -144,7 +150,15 @@ dma_subsys: bus@5a000000 { edma2: dma-controller@5a1f0000 { compatible = "fsl,imx8qm-edma"; - reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */ + reg = <0x5a200000 0x10000>, /* channel0 LPSPI0 rx */ + <0x5a210000 0x10000>, /* channel1 LPSPI0 tx */ + <0x5a220000 0x10000>, /* channel2 LPSPI1 rx */ + <0x5a230000 0x10000>, /* channel3 LPSPI1 tx */ + <0x5a240000 0x10000>, /* channel4 LPSPI2 rx */ + <0x5a250000 0x10000>, /* channel5 LPSPI2 tx */ + <0x5a260000 0x10000>, /* channel6 LPSPI3 rx */ + <0x5a270000 0x10000>, /* channel7 LPSPI3 tx */ + <0x5a280000 0x10000>, /* channel8 UART0 rx */ <0x5a290000 0x10000>, /* channel9 UART0 tx */ <0x5a2a0000 0x10000>, /* channel10 UART1 rx */ <0x5a2b0000 0x10000>, /* channel11 UART1 tx */ @@ -153,8 +167,16 @@ dma_subsys: bus@5a000000 { <0x5a2e0000 0x10000>, /* channel14 UART3 rx */ <0x5a2f0000 0x10000>; /* channel15 UART3 tx */ #dma-cells = <3>; - dma-channels = <8>; - interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + dma-channels = <16>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, @@ -162,11 +184,23 @@ dma_subsys: bus@5a000000 { <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", + interrupt-names = "edma2-chan0-rx", "edma2-chan1-tx", + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-rx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", + "edma2-chan8-rx", "edma2-chan9-tx", "edma2-chan10-rx", "edma2-chan11-tx", "edma2-chan12-rx", "edma2-chan13-tx", "edma2-chan14-rx", "edma2-chan15-tx"; - power-domains = <&pd IMX_SC_R_DMA_2_CH8>, + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, <&pd IMX_SC_R_DMA_2_CH9>, <&pd IMX_SC_R_DMA_2_CH10>, <&pd IMX_SC_R_DMA_2_CH11>, @@ -174,7 +208,11 @@ dma_subsys: bus@5a000000 { <&pd IMX_SC_R_DMA_2_CH13>, <&pd IMX_SC_R_DMA_2_CH14>, <&pd IMX_SC_R_DMA_2_CH15>; - power-domain-names = "edma2-chan8", "edma2-chan9", + power-domain-names = "edma2-chan0", "edma2-chan1", + "edma2-chan2", "edma2-chan3", + "edma2-chan4", "edma2-chan5", + "edma2-chan6", "edma2-chan7", + "edma2-chan8", "edma2-chan9", "edma2-chan10", "edma2-chan11", "edma2-chan12", "edma2-chan13", "edma2-chan14", "edma2-chan15"; |