diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2020-02-29 22:04:43 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2020-03-03 14:21:47 +0800 |
| commit | 086025cc8d385a122089b78f0a146d58392af733 (patch) | |
| tree | 2bb05be6c4d328885eb7ddf6cd385ed6f3b78341 /arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | |
| parent | b84f6b9289a8c44755469618fa033684db914696 (diff) | |
MLK-23424 arm64: dts: imx8dxl: enable legacy enet0 port
Enable legacy enet0 port to support daughter RGMII AR8031
PHY board.
imx8dxl evk board rework:
- Remove U30, R181, R182
- Connect U30.2 -U30.7
- Connect U30.3 ->U30.6
- Change R178/R179 to 1.5K
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 6c80da893d58..6e52a002c9c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -82,6 +82,27 @@ enable-active-high; }; + reg_fec1_sel: regfec1_sel { + compatible = "regulator-fixed"; + regulator-name = "fec1_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>; + regulator-always-on; + status = "disabled"; + }; + + reg_fec1_io: regfec1_io { + compatible = "regulator-fixed"; + regulator-name = "fec1_io_supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + status = "disabled"; + }; + reg_usdhc2_vmmc: usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "SD1_SPWR"; @@ -204,6 +225,14 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0>; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; }; i2c@1 { @@ -413,11 +442,38 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; eee-broken-1000t; + at803x,eee-disabled; + at803x,vddio-1p8v; }; }; }; +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + phy-reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "disabled"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + &usbphy1 { status = "okay"; }; @@ -489,6 +545,27 @@ >; }; + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + pinctrl_flexspi0: flexspi0grp { fsl,pins = < IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 |