diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2020-02-17 18:19:42 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2020-02-18 23:10:50 +0800 |
| commit | 97ed44092c0071c28a02967e9cf5637a96639507 (patch) | |
| tree | 12b1114f09745b3a0407af44ca6662fdee2d9bba /arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | |
| parent | 94829108043e11706aef7c7a70847ec5d7ef68c3 (diff) | |
MLK-23329-05 arm64: dts: add eqos support
Add eqos support for imx8dxl evk board.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 60 |
1 files changed, 58 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index ffe26337c287..5cd10be20344 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -2,6 +2,10 @@ /* * Copyright 2019~2020 NXP */ + +/delete-node/ &enet1_lpcg; +/delete-node/ &fec2; + &usdhc1 { compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; @@ -17,10 +21,62 @@ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; +&enet0_lpcg { + clocks = <&conn_enet0_root_clk>, + <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; +}; + &fec1 { compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec"; }; -&fec2 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; +&conn_subsys { + conn_enet0_root_clk: clock-conn-enet0-root { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "conn_enet0_root_clk"; + }; + + eqos_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_enet0_root_clk>, + <&conn_axi_clk>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>; + bit-offset = <0 8 16 20 24>; + clock-output-names = "eqos_ptp", + "eqos_mem_clk", + "eqos_aclk", + "eqos_clk", + "eqos_csr_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; + + eqos: ethernet@5b050000 { + compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x5b050000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&eqos_lpcg 2>, + <&eqos_lpcg 4>, + <&eqos_lpcg 0>, + <&eqos_lpcg 3>, + <&eqos_lpcg 1>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <125000000>; + power-domains = <&pd IMX_SC_R_ENET_1>; + clk_csr = <0>; + status = "disabled"; + }; }; |