diff options
| author | Teo Hall <teo.hall@nxp.com> | 2020-02-02 17:05:19 -0600 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2020-02-13 07:51:40 +0800 |
| commit | dc329c155d09e496fba9f77611ecc5badf19e4be (patch) | |
| tree | 3e800c3081c6b78c871e5fe3378bd357e20d6101 /arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | |
| parent | 711cce5436e319e88c2f27992431da4175652139 (diff) | |
MLK-23273-5: arm64: dts: Add DT support for imx8dxl
Add DT support for i.MX8DXL.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi new file mode 100644 index 000000000000..43c67be8500f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +&hsio_subsys { + phyx1_lpcg: clock-controller@5f090000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5f090000 0x10000>; + #clock-cells = <1>; + clocks = <&hsio_refb_clk>, <&hsio_per_clk>, + <&hsio_per_clk>, <&hsio_per_clk>; + bit-offset = <0 4 8 16>; + clock-output-names = "hsio_phyx1_pclk", + "hsio_phyx1_epcs_tx_clk", + "hsio_phyx1_epcs_rx_clk", + "hsio_phyx1_apb_clk"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + }; +}; + +&pcieb { + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; +}; |