arm64: dts: freescale: fsl-imx8mm-verdin: add dtbs for v1.1 hw

This reworks the dtsi files to allow to also build device trees for
Verdin iMX8MM V1.1 hardware.

The module level device tree for V1.1 HW is imx8mm-verdin-v1.1.dtsi,
for V1.0 HW the imx8mm-verdin.dtsi is reworked to include the V1.1 dtsi
and then it deletes and adds whatever is different.

This commit incorporates the following HW changes:
- Changed PMIC
- Removal of ADC MAX11607 (The replacement TI TLA2024 is not yet added)
- Removal of external PCIe PHY Clock in favour of SoC provided one
- Prepare for not stuffed security alternatives SE050, ATTPM20P
- Changed pin usage, see below

Pin usage changed from V1.0 to V1.1 HW:
To ease creation of V1.0 and V1.1 device trees move all pin groups,
also wifi and nonwifi ones, into imx8mm-verdin-v1.1.dtsi and change
them as needed in imx8mm-verdin.dtsi for V1.0 HW.

The eMMC reset is now connected to the SD1_RESET_B ball.
Add it to the eMMC pin groups for V1.1.

CTRL_FORCE_OFF_MOCI# used to be controlled by SAI5_RXC in V1.0 HW. In V1.1
HW it is no longer under SW control.
Delete the unused pin group for V1.1.

Wi-Fi_WKUP_WLAN used to be controlled by SD1_RESET_B in V1.0 HW. In V1.1
HW it is controlled by SAI5_RXC.
Update the pin group for V1.1.

Related-to: ELB-3130, ELB-3136, ELB-3150
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Conflicts:
        arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>

1 files changed, 0 insertions, 14 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
index 3be5aa2c6071..c488a4111cdb 100755
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
@@ -3,8 +3,6 @@
  * Copyright 2020 Toradex
  */
 
-#include "imx8mm-verdin.dtsi"
-
 &gpio3 {
 	gpio-line-names = "SODIMM_52",
 			  "SODIMM_54",
@@ -75,15 +73,3 @@
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 };
-
-&iomuxc {
-	pinctrl_tsp: tspgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6			0x140		/* SODIMM 148 */
-			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7			0x140		/* SODIMM 152 */
-			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8			0x140		/* SODIMM 154 */
-			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9			0x140		/* SODIMM 179 */
-			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17			0x140		/* SODIMM 150 */
-		>;
-	};
-};