diff options
author | Fancy Fang <chen.fang@nxp.com> | 2019-11-02 17:05:41 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:09:02 +0800 |
commit | 20517363b04b67a2cbb60761750d7d8c6e296aed (patch) | |
tree | fd2876c8edfbc9aa4b832e0bf4694a0a9ace51e8 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
parent | 5b44f9e58b26e12e381a07a0cbb160a411c29003 (diff) |
arm64: dts: imx8mm: Define resets for LCDIF and DSIM
The dispmix-reset device can be used to control the LCDIF and
DSIM bus reset and clock enable. So define 'resets' property
for both LCDIF and DSIM for this purpose which will be used to
replace 'dispmix_gpr' usage.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 9a70ffa15286..274ca730bc32 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/imx8mm-dispmix.h> #include <dt-bindings/thermal/thermal.h> #include "imx8mm-pinfunc.h" @@ -1090,6 +1091,7 @@ assigned-clock-rate = <594000000>, <500000000>, <200000000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; lcdif-gpr = <&dispmix_gpr>; + resets = <&lcdif_resets>; power-domains = <&dispmix_pd>; status = "disabled"; @@ -1117,6 +1119,7 @@ assigned-clock-rates = <266000000>, <594000000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; dsi-gpr = <&dispmix_gpr>; + resets = <&mipi_dsi_resets>; power-domains = <&mipi_pd>; status = "disabled"; @@ -1324,6 +1327,40 @@ }; }; + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; + }; + }; + rpmsg: rpmsg{ compatible = "fsl,imx8mq-rpmsg"; /* up to now, the following channels are used in imx rpmsg |