diff options
| author | Zhou Peng <eagle.zhou@nxp.com> | 2019-08-28 09:55:03 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:06 +0800 |
| commit | 5215b054194515abc2fea16512cb63d205617d1e (patch) | |
| tree | 6fef9c3a55a006f2b3d1a2c0fb464248d91d2a3f /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | d78d416ca78b10c7aede49f8d0c89ecc1d1d460b (diff) | |
arm64: dts: imx845: add vpu encoder
enable 845 h1 in device tree
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c0faf0f3be47..80df664b4f79 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1180,6 +1180,21 @@ status = "disabled"; }; + vpu_h1: vpu_h1@38320000 { + compatible = "nxp,imx8mm-hantro-h1"; + reg = <0x0 0x38320000 0x0 0x10000>; + reg-names = "regs_hantro_h1"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro_h1"; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>, <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_h1", "clk_hantro_h1_bus"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_H1>,<&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, <800000000>; + power-domains = <&vpu_h1_pd>; + status = "disabled"; + }; + vpu_g1: vpu_g1@38300000 { compatible = "nxp,imx8mm-hantro"; reg = <0x0 0x38300000 0x0 0x100000>; |