diff options
| author | Ella Feng <ella.feng@nxp.com> | 2019-09-06 19:35:28 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:07:31 +0800 |
| commit | 8bbd733e2e51ae22dd94f9739ce602d42c8b00df (patch) | |
| tree | a887b2348406fbe7eddee018f15300c9ec3f5323 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | fc229c0fc130d20edbf7a852d4ef8a2e8146b3ac (diff) | |
arm64: dts: imx8mm: Add GPU device for 8MM
Add gpu in device tree:
arch/arm64/boot/dts/freescale/imx8mm.dtsi
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
Signed-off-by: Ella Feng <ella.feng@nxp.com>
[ Aisheng: remove unecessary new blank line ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 71f63e4a8676..76fac2ff53dd 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1267,4 +1267,40 @@ power-domains = <&vpu_g2_pd>; status = "disabled"; }; + + gpu: gpu@38000000 { + compatible ="fsl,imx8mm-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x8000>, <0x0 0x38008000 0x0 0x8000>, + <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", + "gpu3d_axi_clk", "gpu3d_ahb_clk", + "gpu2d_clk", "gpu2d_axi_clk", + "gpu2d_ahb_clk"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_SRC>, + <&clk IMX8MM_CLK_GPU2D_SRC>, + <&clk IMX8MM_CLK_GPU_AXI>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_GPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <0>,<400000000>,<1000000000>; + + power-domains = <&gpumix_pd>; + + status = "disabled"; + }; }; |