diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-11 13:21:15 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-06-11 10:06:32 +0800 |
| commit | a96d6877756d575c02c83f510c74c081b854bb87 (patch) | |
| tree | 67bddb041c2476a9b984bf3c482a6410436a3f28 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | 11b7bf3e9d6c3badc862c5ade76912e0a493507e (diff) | |
MLK-24012-06 arm64: dts: add imx8m pcie ep support
Add the PCIe EP mode on iMX8MQ/MM/MP platforms.
And enable the EP mode on EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 43bd59015f06..0247ff9b25cf 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1304,6 +1304,27 @@ status = "disabled"; }; + pcie0_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x000400000>, + <0x18000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ |