diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2020-11-17 10:35:11 +0800 |
|---|---|---|
| committer | Fancy Fang <chen.fang@nxp.com> | 2020-11-19 13:51:02 +0800 |
| commit | b2afd6ee3f3d2f179bced041b7711f220a377387 (patch) | |
| tree | 15145d1c55f6318cc71e6fcf38df92b3d94d0e48 /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | d7e6489482b8342d593d1158cbd06419aa7b4b1b (diff) | |
MLK-24998-8 arm64: dts: imx8mm: assign osc_24m to dsi PHY REF clock source
Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim:
use 12MHz for default PHY REF clock), the dsi PHY reference
clock source need to be assigned to osc_24m clock.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 2972241b831ed65f641ccdb80b504cadef0ba591)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 121459b19355..75516614e5bd 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1146,8 +1146,8 @@ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, <&clk IMX8MM_CLK_DSI_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_VIDEO_PLL1_OUT>; - assigned-clock-rates = <266000000>, <594000000>; + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <12000000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; dsi-gpr = <&dispmix_gpr>; resets = <&mipi_dsi_resets>; |