MLK-23372 perf/imx_ddr: correct CLEAR bit definition

ddr_perf_event_stop will firstly call ddr_perf_counter_enable to disable
the counter, and then call ddr_perf_event_update to read the counter value.

When disable the counter, it will write 0 into COUNTER_CNTL[CLEAR] bit
which cause the counter value cleared. Counter value will always be 0
when update the counter.

The correct definition of CLEAR bit is that write 0 to clear the counter
value.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

0 files changed, 0 insertions, 0 deletions