diff options
| author | Xianzhong <xianzhong.li@nxp.com> | 2019-12-19 23:27:25 +0800 |
|---|---|---|
| committer | Xianzhong <xianzhong.li@nxp.com> | 2019-12-20 18:07:38 +0800 |
| commit | 6cc89b1bee762f81665d0b988f49a83bf3e42765 (patch) | |
| tree | 51bc355cf6d277114ae7aadc444aa0772c4061e9 /arch/arm64/boot/dts/freescale/imx8mn.dtsi | |
| parent | e41f1a1fa21c8a2d164ac3fd00126ccaf0dad710 (diff) | |
LF-531-1 arm64: dts: imx8mq/imx8mn: fix gpu setting
move gpu device configuration out of soc subsystem,
gpu parameters exceed soc range and will be skipped:
ranges = <0x0 0x0 0x0 0x3e000000>
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 57 |
1 files changed, 28 insertions, 29 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index a63b27ee4511..dc1093812869 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1131,35 +1131,6 @@ status = "disabled"; }; - gpu: gpu@38000000 { - compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; - reg = <0x38000000 0x40000>, <0x40000000 0x80000000>, <0x0 0x8000000>; - reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq_3d"; - clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, - <&clk IMX8MN_CLK_GPU_SHADER_DIV>, - <&clk IMX8MN_CLK_GPU_BUS_ROOT>, - <&clk IMX8MN_CLK_GPU_AHB>; - clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; - assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, - <&clk IMX8MN_CLK_GPU_SHADER_SRC>, - <&clk IMX8MN_CLK_GPU_AXI>, - <&clk IMX8MN_CLK_GPU_AHB>, - <&clk IMX8MN_GPU_PLL>, - <&clk IMX8MN_CLK_GPU_CORE_DIV>, - <&clk IMX8MN_CLK_GPU_SHADER_DIV>; - assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, - <&clk IMX8MN_GPU_PLL_OUT>, - <&clk IMX8MN_SYS_PLL1_800M>, - <&clk IMX8MN_SYS_PLL1_800M>; - assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, - <600000000>, <600000000>; - depth-compression = <0>; - power-domains = <&gpumix_pd>; - status = "disabled"; - }; - gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -1170,6 +1141,34 @@ }; }; + gpu: gpu@38000000 { + compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu"; + reg = <0x0 0x38000000 0x0 0x40000>, <0x0 0x40000000 0x0 0x80000000>, <0x0 0x0 0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <600000000>, <600000000>; + power-domains = <&gpumix_pd>; + status = "disabled"; + }; + rpmsg: rpmsg{ compatible = "fsl,imx8mq-rpmsg"; /* up to now, the following channels are used in imx rpmsg |