diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2020-11-17 10:41:01 +0800 |
|---|---|---|
| committer | Fancy Fang <chen.fang@nxp.com> | 2020-11-19 13:51:02 +0800 |
| commit | ce8dea542e6d0f6cd93b99625aaa0af4693c7963 (patch) | |
| tree | 261d8c569463682d245101efec44f9cc87b06152 /arch/arm64/boot/dts/freescale/imx8mn.dtsi | |
| parent | b2afd6ee3f3d2f179bced041b7711f220a377387 (diff) | |
MLK-24998-9 arm64: dts: imx8mn: assign osc_24m to dsi PHY REF clock source
Due to commit b3a420c9cf3f (MLK-24998-4 drm/bridge: sec-dsim:
use 12MHz for default PHY REF clock), the dsi PHY reference
clock source need to be assigned to osc_24m clock.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 8e43cd16c8bbfe5b7e3c0fc1e7c3ddf738d8db01)
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 3a061e610db1..5d4c245376b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1088,9 +1088,9 @@ assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, <&clk IMX8MN_CLK_DSI_PHY_REF>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, - <&clk IMX8MN_VIDEO_PLL1_OUT>; + <&clk IMX8MN_CLK_24M>; assigned-clock-rates = <266000000>, - <594000000>; + <12000000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; resets = <&mipi_dsi_resets>; power-domains = <&mipi_pd>; |