MLK-24494-5: arm64: dts: imx8mp: add dts for ov2775 and ov5640 support

Add dts for OV2775 + OV5640 for iMX865-EVK board. OV2775 connect to
CSI port 0 and OV5640 connect to CSI port 1, as bellow:
   OV2775 => CSI1
   OV5640 => CSI2
Board need to rework to support this feature. More info, please
refer to rework guide provided by NXP

Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>

1 files changed, 108 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts
new file mode 100644
index 000000000000..d035e5e5cf35
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-ov2775-ov5640.dts
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx8mp-evk.dts"
+
+&iomuxc {
+	pinctrl_csi1_pwn: csi1_pwn_grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x19
+		>;
+	};
+
+	pinctrl_csi1_rst: csi1_rst_grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19
+		>;
+	};
+};
+
+&i2c2 {
+	/delete-node/ov5640_mipi@3c;
+
+	ov2775_0: ov2775_mipi@36 {
+		compatible = "ovti,ov2775";
+		reg = <0x36>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>;
+		clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
+		clock-names = "csi_mclk";
+		assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
+		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+		assigned-clock-rates = <24000000>;
+		csi_id = <0>;
+		pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+		rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		status = "okay";
+
+		port {
+			ov2775_mipi_0_ep: endpoint {
+				data-lanes = <1 2 3 4>;
+				clock-lanes = <0>;
+				remote-endpoint = <&mipi_csi0_ep>;
+			};
+		};
+
+	};
+};
+
+&i2c3 {
+	/delete-node/ov2775_mipi@36;
+};
+
+&ov5640_1 {
+	pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>;
+	csi_id = <1>;
+
+	status = "okay";
+};
+
+&cameradev {
+	status = "okay";
+};
+
+&isi_0 {
+	status = "disabled";
+};
+
+&isi_1 {
+	status = "okay";
+};
+
+&isp_0 {
+	status = "okay";
+};
+
+&dewarp {
+	status = "okay";
+};
+
+&mipi_csi_0 {
+	status = "okay";
+
+	port@0 {
+		endpoint {
+			remote-endpoint = <&ov2775_mipi_0_ep>;
+			data-lanes = <4>;
+			csis-hs-settle = <16>;
+		};
+	};
+};
+
+&mipi_csi_1 {
+	status = "okay";
+};