diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-02-05 22:46:16 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-02-13 10:40:17 +0800 |
| commit | 13d9a2b6e34954082d1f8394d80736faf76b9b54 (patch) | |
| tree | 56c69da14cb1d8bbadb21e523514c45d2456878f /arch/arm64/boot/dts/freescale/imx8mp-evk.dts | |
| parent | dc329c155d09e496fba9f77611ecc5badf19e4be (diff) | |
MLK-23303-1 dts: arm64: add the pcie support on imx8mp
Add the PCIe support on iMX8MP.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <Fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-evk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 291b6050c30a..507d1dfec88d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -543,6 +543,28 @@ status = "okay"; }; +&pcie{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + ext_osc = <0>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_PCIE_AUX>, + <&clk IMX8MP_CLK_PCIE_PHY>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, + <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL2_50M>; + status = "okay"; +}; + +&pcie_phy{ + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -805,6 +827,14 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B 0x61 /* open drain, pull up */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 + >; + }; + pinctrl_pmic: pmicirq { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 |